The present invention relates to a vector processor, and more particularly to a vector processor which is suitable for use in realizing an ultra high speed machine cycle in a super computer.
In general, in order to enhance performance of a super computer, it is most effective to provide a plurality of pipeline arithmetic and logic units and a plurality of vector registers to, in parallel, process vector data among non-related instructions and rapidly transfer the vector data to be processed in parallel from the vector registers to the pipeline arithmetic and logic units and from the arithmetic and logic units to the vector registers so that the machine cycle is reduced.
In a repetitive operation, which is a feature of the vector operation, there are many cases where a vector register which retains a vector operation result supplies an operand in the next instruction execution. Thus, in order to allow chaining to simultaneously read the operand data and write the operation result for the vector register having one logical address, a RAM, which constitutes the vector register, is constructed to have two independently addressable bank arrays. One of the banks holds all even-numbered elements of the vector data while the other bank holds all odd-numbered elements of the vector data so that the writing and the reading for each bank are attained at a clock rate of the machine cycle. Such a vector processor is disclosed in JP-A-58-114274. Further, JP-A-59-77574 discloses a high speed technique for non-banked vector registers.
In constructing the vector registers by the 2-bank RAM and reading and writing the RAM at the clock rate of the machine cycle, factors which determine the clock rate of the machine cycle are a write time (pitch) and a read time (pitch) (address access time) of the RAM which holds the vector data More specifically, the write pitch, which is defined by a sum of a set-up time, a write pulse width and a hold time, is dominant in determining the clock rate since it takes 1.5 times as long time, as a read pitch for an address input-driven case. Where an ultra high speed compound semiconductor (GaAs, HEMT) is used, this trend remains unchanged as a property of a memory circuit. On the other hand, as seen from the prior art described above, it is essential in enhancing the performance of the vector processor to raise the clock rate of the machine cycle. In the 2-bank RAM vector registers of the prior art, however, the write clock rate and the read clock rate are equal. Thus, where the read pitch is faster than the clock rate but the write pitch is slower than the clock rate, the write pitch is a significant factor which restricts the enhancement of the clock rate of the machine cycle. Particularly when an ultra high speed RAM having an access time of less than 1 nanosecond is used, the read pitch cannot be efficiently utilized.